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Computer Science Emerging Technologies

cs.ET Watch Emerging Technologies

Thursday 10 September

Emerging Technologies

From Grid to Chip: Power Architecture, Stability, and Flexibility of AI Data Centers

Yubo Song, Rui Kong, Takuro Umihara et al. (+3 more)

The rapid growth of artificial intelligence (AI) computing is transforming data centers into large, dynamic electrical loads. Their deployment is primarily constrained by energy availability and grid-connection capacity, which is further aggravated by the ability of power-delivery architectures, control systems, and computing workloads to operate reliably during fast grid disturbances. This article presents a technological perspective on AI data centers as grid-interactive computing systems. First, it reviews grid-integration bottlenecks, evolving connection policies, grid-code requirements, which has fostered new technological trends via spatio-temporal flexibility available through workload orchestration, cooling systems, on-site resources, and energy storage. Second, it maps the evolution of power-delivery architectures from medium-voltage grid interfaces to chip-level, discussing higher-voltage DC distribution, solid-state transformers, wide-bandgap devices, advanced chip-level power delivery, and liquid cooling. Third, it establishes a three-level stability framework spanning rack-level DC-bus dynamics, facility-level converter interactions, and system-level grid-coupled behavior. The framework connects dominant instability mechanisms, including constant power load effects, impedance interactions, forced oscillations, and operating-mode transitions, with suitable modeling, assessment, and mitigation approaches. Synthesizing these topics, this article highlights grid-to-chip co-design as a central requirement for scalable AI infrastructure, linking computing workloads, power-delivery systems, energy buffers, and grid operation.
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All authors Yubo Song, Rui Kong, Takuro Umihara, Pooya Davari, Frede Blaabjerg, Subham Sahoo

Emerging Technologies · Cross-listed from cs.CR

PHAT: PHotonic Accelerator for TFHE

Guowei Yang, Farbin Fayza, Beren Aydoğan et al. (+3 more)

Fully Homomorphic Encryption (FHE) enables secure computation on encrypted data, making it a promising solution for privacy-preserving applications in the cloud. Among various FHE schemes, FHE over the Torus (TFHE) stands out due to its support for arbitrary operations. However, its high computation and communication overhead, particularly in the Fast Fourier Transform (FFT) operations required during bootstrapping, limits its practicality for real-world applications. Conventional electronic accelerators struggle to achieve sufficient throughput due to the limitations of technology scaling and the memory-wall problem. To address these challenges, we propose PHAT, a PHotonic Accelerator for TFHE leveraging Optically-addressed Phase-Change Memory (OPCM). OPCM-based processing-in-memory systems offer high computation and communication throughput, making them well-suited for accelerating FFT operations in TFHE. However, directly mapping FFT to OPCM presents challenges such as high-precision analog computation and the high latency and energy cost of programming OPCM cells. To overcome these challenges, we introduce a novel electro-photonic accelerator architecture optimized for TFHE, featuring OPCM-based FFT units, a twiddle-stationary dataflow tailored for OPCM, and a scheduling mechanism to maximize the utilization of the FFT units. PHAT delivers $2.14\times$–$5.10\times$ speedup across four real-world TFHE workloads against the state-of-the-art ASIC accelerator. Our approach significantly enhances the performance of TFHE applications, paving the way for practical and efficient homomorphic encryption in cloud computing.
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All authors Guowei Yang, Farbin Fayza, Beren Aydoğan, Carlos A. Ríos Ocampo, Ayse K. Coskun, Ajay Joshi

Emerging Technologies · Cross-listed from quant-ph

Generative Replay Mitigates Sample Starvation in Quantum Architecture Search

Akash Kundu, Amit Kumar Jaiswal, Sebastian Feld et al. (+1 more)

Reinforcement learning (RL) can automate quantum architecture search, but its scalability is limited when useful circuit trajectories become rare in the rapidly expanding search space. Existing replay mechanisms reuse observed transitions; the proposed learned model produces additional predicted one step transitions from real state-action seeds. Here we introduce GenQAS, a tensor network-guided RL framework that combines a fixed matrix product state warm-start with prioritized generative replay. A learned local transition model generates synthetic circuit transitions on demand and mixes them with real experience during Double Deep Q-Network updates. Under a random exploration analysis, near ground state circuits occupy a rapidly shrinking region of the accessible state space. We investigate whether real data anchored synthetic replay can improve the effective training signal in this regime. Across chemical Hamiltonian benchmarks from 6 to 12 qubits, GenQAS improves fixed-budget success probability and identifies compact circuits at competitive energy error. At 12 qubits, it improves final success probability by up to $7.0\times$ over passive replay. On a 15-qubit transverse field Ising model, GenQAS increases success probability from $12\%$ to $21\%$. In a noisy 6-qubit BeH$_2$ transfer experiment, generative replay reduces the steps to chemical accuracy by $92.7\%$. These results show that generative replay can mitigate sample starvation in quantum architecture search and support more resource efficient circuit discovery.
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All authors Akash Kundu, Amit Kumar Jaiswal, Sebastian Feld, Prayag Tiwari

Emerging Technologies · Cross-listed from cs.CV

Beyond Benchmarks: Using VLMs to Reveal Systematic Classification Failures Under Real World Conditions

Dieuwertje Alblas, Alma M. Liezenga, Jan Erik van Woerden et al. (+3 more)

Verification and validation (V&V) of classification models is crucial to enable a wide range of sensor processing applications. Currently, the V&V process relies on time-consuming manual inspection of erroneous samples to find meaningful patterns. This work explores the use of Vision Language Models (VLMs) to speed up this laborious process. VLMs are trained to embed images into a semantically meaningful vector representation, from which human-interpretable systematic errors can be distilled. Deploying such VLM-based methods in a defence context introduces two major challenges: (1) the defence domain is underrepresented in the training data of VLMs, and (2) surroundings and context are less diverse than for other domains. This study provides an initial assessment of the suitability of VLM-based methods for V&V of defence applications. We propose a VLM-based error slice detection (ESD) method that independently groups and labels systematic errors made by a classification model. We demonstrate that this method is able to identify operationally-relevant artificially added perturbations in a non-military dataset. In a military context, our method clusters and describes images based on their surroundings, but also exhibits overlap between cluster descriptions. We further investigate the difference in embedding variation between our military and non-military dataset, which remains a topic of interest. Although the results do not yet warrant fully automated V&V through VLM-based ESD, they show that VLMs could be used to accelerate V&V processes in the future.
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All authors Dieuwertje Alblas, Alma M. Liezenga, Jan Erik van Woerden, Fedor Taggenbrock, Dalia Aljawaheri, Klamer Schutte

Emerging Technologies · Cross-listed from cs.MA

But How Would AI Agents Run a Town's Economy?

Sajal Regmi, Siddhartha Pudasaini and Chetan Phakami Pun

We placed 100 memory-equipped large language model (LLM) agents in charge of a closed, money-conserving spatial economy on real Pokhara Lakeside geography (earning wages, running businesses, setting prices) and ran this multi-agent simulation for up to 26 simulated weeks, well past the 1-2 weeks typical of agent-society studies. Across 91 validated runs (2.44M agent decisions, 21.5B tokens), the money stops moving, in a specific and measurable way. A 12x tourist demand shock raises business revenue 4.62x ($p<0.001$), which we decompose exactly into a 1.50x extensive margin (more businesses trading) and a 3.07x intensive margin (more revenue each). Monetary transmission stops there. Wages move 1.03x ($p=0.42$); 0.3% of 3,981 menu items are ever repriced ($p=0.47$). A randomized cash transfer (NPR 5,000 to 20 of 100 agents) shows the same pattern from the opposite direction: 96.7% is still held 311 pulses later, marginal propensity to consume 3-4% by two independent measures, indistinguishable from zero. The wealth distribution is consequently near-frozen at the horizon this literature uses ($\rho=0.964$ over 2 simulated weeks), but not frozen. $\rho$ falls to 0.832 at 12 weeks and 0.752 at 26, a horizon-dependence no short study can see. Matched ablations show which knob actually matters. Swapping the backing LLM moves every outcome we measure ($p=0.0039$); deleting agents' memory moves none of them detectably. A purely social tool fails 94-97% of the time across two model families, compared with ~96% success on economic tools, with no measurable shift away from it. Every headline number is verified twice, by a live validator and by an offline recomputation that reconciles each agent's wealth against its own signed transaction history, and we release the full run corpus for reanalysis.
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Wednesday 9 September

Emerging Technologies

Fractional-order hardware for neuromorphic computing: Is the order really the problem?

Christof Teuscher

Does a neuromorphic system need a true power-law memory kernel, and if so, can anyone build one? Neuromorphic systems process signals spanning many timescales at once, from milliseconds to tens of seconds. Integer-order circuits buy each additional timescale with an additional state variable. Fractional-order dynamics offer a different bargain: one operator whose power-law kernel carries a continuum of timescales, tuned by one parameter, the order alpha. A fractional derivative is non-local, so evaluating it costs storage and arithmetic that grow with the retained history, where an integer-order derivative costs a constant. This review organizes the hardware literature around that cost. We derive the retained history needed to hold the truncation error below a tolerance epsilon, show that it scales as epsilon^(-1/alpha), and set beside it a second and independent limit on the direct form: in fixed point the weights themselves underflow, so word length caps the usable history however long the buffer is. The two limits move at very different rates with the order, and where they cross decides whether a word length can serve an order at all. We use both to sort published hardware into three strategies, note a fourth the numerical literature has developed and this hardware has not, and survey digital, analog and device work. Along the way we ask whether the field is worried about the right obstacle. It is not. Fabricated constant-phase devices already span the orders two groups identify as task-optimal, so the order gap has largely closed, leaving a residual gap near 0.1 and at the lower order describing cortical adaptation. What remains is a frequency-band gap of about three decades at the low end. That corner is not empty, since double-layer electrodes work there, but every device in it is discrete, and no integrable thin-film element has been characterized there.
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Emerging Technologies · Cross-listed from quant-ph

Fidelity-Aware Scheduling of Quantum Circuits on Multi-QPU Systems

Innocenzo Fulginiti, Antonio Tudisco, Salvatore Zammuto et al. (+7 more)

High Performance Computing-Quantum Computing (HPCQC) platforms expose multiple Quantum Processing Units (QPUs) that may differ in size, topology, native gates, and noise characteristics. For current noisy devices, errors compound along the compiled circuits quickly, and minimizing them, that is, maximizing the circuits' execution fidelity, is essential for reliable results. Fidelity depends on the compilation to a specific target device: the same high-level circuit may produce different executables and, therefore, different expected fidelities across QPUs. We present a low-overhead fidelity-aware scheduling framework for multi-QPU systems based on a Graph Neural Network (GNN) that estimates, before compilation, the expected fidelity of each circuit on each available QPU. Then, a tunable scheduler uses these estimates to control the trade-off between execution fidelity and parallelism. Results show that this framework allows for approximating an exhaustive fidelity-based assignment, saving computational resources compared to a brute-force approach that compiles each circuit on every device.
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All authors Innocenzo Fulginiti, Antonio Tudisco, Salvatore Zammuto, Patrick Hopf, Deborah Volpe, Helmut Seidl, Giovanna Turvani, Robert Wille, Christian B. Mendl, Martin Schulz

Emerging Technologies · Cross-listed from cs.AR

HBFSim: Fast and Faithful Simulation of High-Bandwidth Flash Under Real GPU Execution

Yanpeng Hu, Yiwei Yang, Yuanwu Zhu et al. (+3 more)

High-Bandwidth Flash (HBF) places high-capacity NAND beside HBM to relieve the memory-capacity bottleneck of LLM inference, yet its system-level behavior cannot be evaluated before hardware becomes available. Cycle-level GPU simulators are too slow for production-scale models. Trace replay has a further shortcoming: it cannot capture the allocation, migration, and execution changes induced by different HBM-HBF configurations. Our key insight is that HBF need not be evaluated by simulating the GPU: only the program-visible effects of HBF need to be modeled. And only a real LLM workload running on real hardware can answer the arguments about HBF. Hence the modeled service has to be injected into that running program, and the injection must not destroy the GPU concurrency that would hide the original I/O latency. We present HBFSim, an open-source HBF simulator that executes LLM workloads on a real GPU while modeling HBF timing, thermal, and other behaviors online. HBFSim rewrites the PTX of the workload's kernels and routes accesses inside a registered address range into the HBF simulator. It supports asynchronous TMA transfers and capacities beyond physical GPU memory. HBFSim leaves the model's run unaffected across ordinary-memory, TMA, and capacity-mode tests. The delay it injects matches the delay requested to within 0.152%. We also design a coupled thermal module that puts HBF, HBM, and the GPU in one advanced package, which is important for answering how severe the hot throttling problem becomes after HBF runs for a long time. Experiments with Qwen3-30B show how package heating, HBM-HBF allocation, and shared MoE demand jointly constrain the design space of future HBF accelerators. The source code of HBFSim is available at https://github.com/SlugLab/hbfsim/.
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All authors Yanpeng Hu, Yiwei Yang, Yuanwu Zhu, Yusheng Zheng, Andi Quinn, Wei Zhang

Emerging Technologies · Cross-listed from cs.HC

AppetiteCheck: Feasibility of Momentary Vagus Nerve Stimulation as an Implicit Intervention for Eating Behavior

Tan Gemicioglu, Jas Brooks, Pedro Lopes et al. (+1 more)

Overeating and emotional eating are common health issues that affect people even without an eating disorder. The vagus nerve plays a critical role in the gut-brain axis, and implanted vagus nerve stimulators have been associated with reduced appetite. In this paper, we propose transcutaneous cervical vagus nerve stimulation (tcVNS) as a ubiquitous system to provide immediate, low-effort intervention during an eating episode. In a study with 24 participants, we evaluated a mobile, handheld tcVNS device during a single episode of distracted snacking. We found that participants ate 9.6% less and 23.6% more slowly during vagus nerve stimulation than during sham stimulation. Post-snacking satiety was the same in both conditions, while heart rate was lower during vagus nerve stimulation. The stimulation was described as subtle and barely noticeable. Overall, these results provide evidence for the feasibility of non-invasive vagus nerve stimulation as a low-attention intervention for managing eating behavior – one that can be packaged inside ubiquitous interactive systems. As such, we extend the design space of implicit interfaces toward physiological intervention, motivating future ubiquitous systems that pair eating-related sensing with low-attention interventions.
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All authors Tan Gemicioglu, Jas Brooks, Pedro Lopes, Tanzeem Choudhury

Emerging Technologies · Cross-listed from cs.SE

The Vibe Shift in Software Engineering: Evaluating AI-Led Conversational Programming for Performance, Cognition, and Responsible Adoption

Sales G. Aribe Jr. and Louie Jay S. Labastida

This study evaluates Vibe Coding, an emerging AI-led conversational programming paradigm that enables developers to generate software through natural-language interaction with large language models. Using a mixed-methods design, the study assessed performance efficiency, cognitive implications, and responsible adoption in comparison with traditional and AI-assisted coding environments. Thirty participants, including professional developers and advanced computing students, completed equivalent programming tasks under three experimental conditions. Quantitative data were analyzed using descriptive statistics and repeated-measures ANOVA, while qualitative data were examined through thematic analysis. Results show that vibe coding significantly improved development efficiency, reducing task completion time by 27% compared with traditional coding and 12% compared with AI-assisted coding. However, these gains were accompanied by lower maintainability indices and higher security vulnerabilities, indicating trade-offs in software quality. Usability results yielded a good rating (SUS = 71.4), while cognitive workload remained moderate (NASA-TLX = 55.5), reflecting reduced syntactic effort but increased linguistic reasoning. Thematic analysis identified trust calibration, loss of control, cognitive adaptation, and prompt-engineering strategy as key constructs. Notably, perceived loss of control was associated with increased security risks due to reduced transparency and validation of AI-generated outputs. Based on these findings, the study proposes a three-pillar framework for responsible adoption: hybrid integration of human and AI capabilities, human oversight and transparent accountability, and context-aware deployment. Overall, vibe coding enhances productivity but requires critical oversight, reinforcing its role as a transformative yet transitional paradigm in software development.
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Tuesday 8 September

Emerging Technologies

E-ALS: Approximation-Potential-Aware E-Graph Rewriting for Approximate Logic Synthesis

Bin Sun, Jianan Mu, Jiaxi Zhang et al. (+4 more)

Approximate logic synthesis (ALS) improves circuit power, performance, and area by trading exact correctness for bounded functional error. However, existing structural ALS methods largely overlook structural bias: even functionally equivalent netlists can expose markedly different approximation opportunities and lead to substantially different outcomes under the same downstream ALS flow. Our experiments show that this effect can induce final area gaps of up to 42.77%. To unlock this opportunity, we propose E-ALS, an e-graph-based framework for approximation-aware structural search. E-ALS combines Function-Reduced Saturation, an ALS-coupled surrogate, search-based extraction, and budget-guided refinement to identify approximation-friendly equivalent structures. Experiments on well-established arithmetic and logic benchmarks show that E-ALS achieves additional area reductions of 3.2 and 7.0 percentage points under maximum Hamming-Distance and Error-Distance constraints, respectively. Code is available in https://github.com/ZenuSunB/Ecompile.git.
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All authors Bin Sun, Jianan Mu, Jiaxi Zhang, Rengang Zhang, Zhiteng Chao, Jing Ye, Huawei Li

Emerging Technologies

OmniEye: Efficient Multimodal Forensic Video Intelligence for Law-Enforcement Body-Worn Cameras

Mamadou K. Keita, Angela Srbinovska, Anita Srbinovska et al. (+12 more)

We introduce OmniEye, a multimodal video intelligence system for law-enforcement training and review (source code available on request to verified law-enforcement and public-safety agencies). OmniEye ingests body-worn camera footage and perceives every 30-second window jointly across video and audio with one multimodal foundation model. It then stores the model's structured output in an embedded SQLite database with BM25 full-text search. Officers can question the footage through an agent that writes structured queries, retrieves candidate windows, and re-perceives them with the model before it may cite them. The whole system runs on one 16 GB GPU with a 4-bit quantization-aware-trained model, and it also scales to full bf16 precision on a multi-GPU cluster.
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All authors Mamadou K. Keita, Angela Srbinovska, Anita Srbinovska, Nishka Desai, Isabella Zicari, P. Kwaku Sanaah-Faried, Sanjay Charitesh Makam, Wyatt Auten, Vivek Senthil, Hannah Desnick, Jonathan Bateman, Adrian Martin, Christopher Homan, John McCluskey, Ernest Fokoué

Emerging Technologies

A Quantum-Inspired Approach to MaxCut Based on Sparse Walsh/Pauli-Correlation Encoding

Cesar Augusto do Amaral, Marcos Vinicius Reballo, Marcus Ritt et al. (+2 more)

We present a quantum-inspired Walsh/PCE solver for MaxCut based on sparse Pauli-correlation encodings. Instead of assigning one qubit or one variable to each graph vertex directly, the method represents relaxed binary variables through expectation values of diagonal Pauli/Walsh observables. These correlators are computed classically from sparse Walsh autocorrelations, producing a compact differentiable relaxation of the MaxCut objective. We evaluate the method on selected Gset instances, G1, G6, G12, and G18, and compare it with random search and tabu search over 10 independent seeds. The proposed model uses $801$ active parameters, corresponding to only $0.306\%$ of the full Walsh space over $18$ qubits. After a final bitflip local search, Walsh/PCE achieves approximation ratios of $0.99033 \pm 0.00226$ on G1, $0.95647 \pm 0.01604$ on G6, $0.96007 \pm 0.00951$ on G12, and $0.92964 \pm 0.02202$ on G18, outperforming both baselines on all tested instances. The method also yields the lowest average runtime in all cases. These results suggest that sparse Walsh/PCE representations provide an efficient quantum-inspired route for MaxCut and may be further extended to hardware-based estimation of Pauli/Walsh correlators.
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All authors Cesar Augusto do Amaral, Marcos Vinicius Reballo, Marcus Ritt, Alexsandro Santos da Rosa Júnior, Fernando Augusto Caletti de Barros

Emerging Technologies

OTTER - Two Transistor - One RRAM Architecture for Reliable In-Memory-Computing in 28 nm CMOS Technology

Yang Chen, Daniele Storelli, Xinyi Zhao et al. (+20 more)

This work presents OTTER, a 28 nm CMOS platform co-integrated with TaOx-based valence-change mechanism (VCM) RRAM, demonstrating a two-transistor-one-memristive-device (2T1R) architecture for reliable in-memory computing. The 2T1R cell combines a low-drive-current (LD) transistor and a high-drive-current (HD) transistor in parallel, providing dedicated bias paths for SET programming and RESET operation, respectively. Through systematic experimental and simulated comparison of various transistor-pairing configurations using the physical compact model JART VCM Rth, design guidelines for transistor sizing are derived, establishing the minimum RESET transistor W/L required for complete RESET as a function of the SET current compliance. The 2T1R cell is further characterized under pulse-based programming, demonstrating multilevel analog conductance tuning with narrow, well separated conductance states across six programmable levels. An analog content-addressable memory (aCAM) design based on the same 2T1R cell is additionally analyzed at the circuit level, evaluating trade-offs between top- and bottom-connected RRAM comparator configurations. A hardware implementation of compute-in-memory (CIM) multiply-and-accumulate (MAC) operations is further demonstrated on a 15 x 15 2T1R crossbar array.
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All authors Yang Chen, Daniele Storelli, Xinyi Zhao, Ankit Bende, Paul-Philipp Manea, Oliver Artner, Arun Ashok, Kay Winterberg, Godwin Paul, Siyuan Jia, Christian Roth, Sabitha Kusuma, Michael Schiek, Vikas Rana, Dirk Wouters, Stephan Menzel, Andre Zambanini, Christian Grewing, Stefan Wiefels, Susanne Hoffmann-Eifert, John Paul Strachan, Stefan van Waasen, Regina Dittmann

Emerging Technologies

OntoKG-EQ: A provenance-grounded, competency-question-governed knowledge graph for auditable analyst querying

Furqan Nasir, Muhammad Atif Saeed, Muhammad Ehsan et al. (+2 more)

Analysts in emerging equity markets keep answering the same questions. Did fundamentals match the market's response? How does the local currency co-move with returns? Which firms outperform sector and benchmark, and which disclosures coincide with abnormal trading? These answers come from ad-hoc spreadsheets that are hard to reproduce, audit, or trust. We present OntoKG-EQ, a knowledge-based system that makes such queries reproducible, evidence-linked, temporally explicit, valid, and inspectable. It couples a bounded, competency-question-governed core ontology with a provenance-aware knowledge graph in which every class, property, shape, and metric is justified by one of five frozen questions. The system materialises market data into the graph, computes the metrics, validates its structure against declarative shape constraints, answers each competency question with a graph query, derives typed findings, and generates an explanation tracing each result to its observations, evidence, sources, and provenance. We evaluate on curated datasets from three emerging markets (Pakistan, Malaysia, Indonesia). Once each market's data is mapped into the common schema, the ontology, shapes, queries, and rules are reused unchanged. A relational-database baseline shows the graph changes no analytics. Its value is governance, provenance, and self-explaining structure. Because answers are rendered deterministically from the validated graph, their consistency with it is guaranteed by construction. Used as a reference, the system measures how consistently eight open language models transcribe the same evidence (provenance coverage 0.00 to 1.00). A study with a 17-participant convenience panel finds the evidence bundle significantly increased perceived trust and completeness. Code and data are openly released.
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All authors Furqan Nasir, Muhammad Atif Saeed, Muhammad Ehsan, Sher Jeel Ahmad, Abdul Moiz Altaf

Emerging Technologies

Movable-Element STAR-RIS for 6G: From Programmable Propagation to Programmable Geometry

Wali Ullah Khan and Muhammad Adil

Reconfigurable intelligent surfaces (RISs) make the wireless propagation environment programmable, while simultaneously transmitting and reflecting RISs (STAR-RISs) extend this capability to users located on both sides of a surface. However, conventional STAR-RIS architectures retain a fixed physical geometry after deployment. Movable-element STAR-RIS (ME-STAR-RIS) introduces an additional spatial degree of freedom by allowing the surface elements to reposition within prescribed regions while maintaining electronic control of their transmission and reflection responses. This combination of electromagnetic and geometric reconfiguration can alter propagation distances, multipath combinations, spatial correlation, interference, near-field focusing, and sensing geometry. This article presents a system-level perspective on ME-STAR-RIS through the concept of programmable geometry. We discuss its operating principles, movement architectures, and promising applications in communications, security, near-field systems, sensing, and high-mobility networks. A representative case study comparing optimized fixed and movable STAR-RIS architectures illustrates measurable spectral-efficiency gains from limited local displacement and the resulting saturation behavior. Finally, key hardware, channel-acquisition, electromagnetic, energy, reliability, and control challenges are discussed toward practical ME-STAR-RIS deployment.
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Emerging Technologies · Cross-listed from cs.AI

Vision: Data-Centric Anchoring for Robust and Interpretable Agentic AI

Arun Vignesh Malarkkan, Xinyuan Wang and Yanjie Fu

Agentic AI systems built on large language models fail in two persistent ways that scaling does not fix: they break under distribution shift, and they cannot explain the decisions they make. We argue these are co-symptoms of one structural deficiency in the data lifecycle that governs how agents are trained, evaluated, and deployed. Observational interaction logs record what an agent did, not what it would have done otherwise. They encode spurious correlations without controlled variation, so they lack the counterfactual structure needed to separate causal signal from coincidence or to validate an explanation. No model-centric method can recover invariances the data never contained. We present Data-Centric Anchoring: robustness and interpretability should be engineered into the data environment, not extracted from models after training. Our central contribution is the Data-Centric Agentic Loop, a four-stage framework of Curate, Augment, Constrain, and Attribute. The ordering is structural, not stylistic. Curation precedes augmentation because generative models amplify whatever bias they are trained on. Augmentation precedes constraint because invariance objectives are vacuous without variation across environments to be invariant to. Attribution closes the loop, converting observed failures into targeted data interventions for the next iteration. Each stage manufactures the preconditions of the next, which makes the loop self-correcting rather than merely sequential. We ground the framework in a failure-driven taxonomy that links four core failure modes to the data lifecycle: spurious feature reliance, distribution-shift fragility, uncertainty miscalibration, and explanation unfaithfulness. We close with the limits of this approach and the open problems that stand between it and practical deployment at scale.
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Monday 7 September

Emerging Technologies · Cross-listed from cs.AR

A 28nm 27,648-Spin Multichip Digital Ising Accelerator with Pegasus Connectivity

Tong Wu, Atharva Raut, Ian Khor et al. (+10 more)

We report a 28 nm four-chip Ising accelerator with 27,648 spins, degree-15 Pegasus connectivity, and 10b coefficients. Boundary-state streaming overlaps interchip transfers with spin updates, achieving 98.03% simulated weak-scaling efficiency. At 140 MHz, the four-chip system delivers 30.24G peak updates/s at 1.2 pJ/update including I/O power, with 11.5$\times$ the throughput and approximately one-quarter the logic-plus-SRAM area per spin of a prior 28 nm multichip design. We demonstrate MaxCut, spin glass, frustrated loops, factorization, and 3SAT.
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All authors Tong Wu, Atharva Raut, Ian Khor, Ziyad Alswaidan, Ting-Yu Lee, Hongchang Kuang, Navid Anjum Aadit, Anand Raju, Dhruv Chinmay, Siddharth Das, Ken Mai, Kerem Camsari, Tathagata Srimani

Emerging Technologies · Cross-listed from quant-ph

Toward Fault-Tolerant Variational Optimization: QAOA under [[4,2,2]] Error Detection

Matteo Robert Child, Emanuele Dri, Giacomo Vitali et al. (+2 more)

We present a partially fault-tolerant implementation of QAOA based on the $[[4,2,2]]$ error-detection code, targeting the Max-Cut problem on a square graph. Our main contribution is a novel ancilla-mediated logical $R_{ZZ}$ gate enabling interactions between qubits in different $[[4,2,2]]$ blocks. We evaluate unencoded and encoded circuits under five noise models, with both all-to-all and grid-routed connectivity, using the Cirq and qsimcirq frameworks with parallel CPU execution. Post-selection on stabilizer measurements consistently improves the probability of sampling optimal bitstrings, with five measurements providing the strongest benefit. These results support error-detection as a practical near-term strategy for improving the quality of variational quantum algorithms.
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All authors Matteo Robert Child, Emanuele Dri, Giacomo Vitali, Chiara Vercellino, Alberto Leporati

Emerging Technologies

Fast simulation of nonlinear deep resistive networks for energy-based computation

Filip Osana, Julie Grollier and Damien Querlioz

Deep resistive networks are electronic energy-based systems in which computation is performed by the steady-state voltages of nonlinear circuits. Nonlinear devices enable expressive input-output transformations, but make the circuit equilibria costly to compute during simulation and training. Recent coordinate-descent solvers have achieved large speedups over SPICE-class circuit simulators, but only for nonlinearities modeled as ideal-diode models. This mathematical simplification is not sufficient for practical analog circuits. Here we extend coordinate-descent simulation to realistic monotone nonlinearities, including Shockley diodes, antiparallel diode pairs, and piecewise-linear current-voltage characteristics. With neighboring voltages fixed, each node update remains a scalar Kirchhoff-law solve. Single-exponential characteristics admit closed-form Lambert-(W) updates, while more general monotone characteristics can be handled with scalar root-finding methods. Across networks with one to three hidden layers and hidden widths from 64 to 1024, the solver reproduces matched SPICE steady-state voltages with relative $L_1$ errors below $1.1\times10^{-4}$ for 90% of validation samples, while achieving speedups up to $(1.7\times10^3)$. We further train a $1568\times100\times20$ double-Shockley network on MNIST, reaching about 3.0% test error and reducing the per-epoch training time by roughly $4.4\times10^2$. Together, these results establish a practical route to the circuit-level design and training of large-scale analog energy-based systems incorporating realistic nonlinear devices.
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Emerging Technologies · Cross-listed from quant-ph

Asymmetric quantum error correction efficiently tackles application-specific noise effects

Abhishek Yadav, Peter K. Schuhmacher and Michael Epping

Noise is a major challenge for current quantum computers. It can be broadly categorized into bit-flip and phase-flip errors. These two types do not necessarily affect the executed algorithm, thus also the application, in the same way. We illustrate this general effect for the example of the quantum approximate optimization algorithm (QAOA) applied to a small instance of the flight-gate assignment (FGA) problem. We compare bit-flip and phase-flip Pauli noise under both layer-level and gate-level noise models, using two circuit decompositions of the same ideal QAOA unitary: a CNOT-based decomposition and a native-$R_{ZZ}$ decomposition. In the simulations, bit-flip noise produces the larger degradation in the performance of the quantum optimization. The asymmetry is most visible in the layer-level and native-$R_{ZZ}$ simulations. We explain this by how the errors affect mixing, final measurements, and how they propagate inside the circuit. We then exploit these insights to tackle noise particularly efficiently using asymmetric error-correcting codes. As an illustration, we use the quantum parity code (QPC), a generalization of the 9-qubit Shor code, and show that a smaller asymmetric code can achieve nearly the same improvement as a larger symmetric choice. This demonstrates that error-correction resources should be assigned not only according to physical error rates, but also according to how strongly each error channel affects the application. As a result, asymmetric quantum error correction proves useful even in cases where the noise model is symmetric. Finally, we discuss how information about the noise obtained through calibration can be exploited in our approach.
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Emerging Technologies · Cross-listed from quant-ph

QCxSimulation: Scatter-Aware X-Ray Projection Radiography via Discrete-Time Quantum Walks

Anja Heim, Theobald Fuchs, Thomas Lang et al. (+4 more)

X-ray projection radiography is a non-invasive imaging technique used in medical diagnostics and industrial inspection. The simulation of X-ray projections is commonly used to optimise acquisition protocols and improve image quality before performing costly scans. Classical photon transport simulations that include realistic X-ray scattering physics are computationally expensive because they require the sampling of a large number of distinct scattering paths. This limits the practical exploration of parameter spaces such as beam energy. Quantum computing offers the potential to solve high-dimensional problems faster by making use of quantum properties such as superposition. This work introduces a discrete-time quantum walk algorithm that simulates the transport of X-ray photons through heterogeneous volumes. It approximates the physics of X-ray projection radiography, including processes such as photoelectric absorption and higher-order scattering, including Compton and Rayleigh scattering. The quantum walk encodes all admissible photon paths into a single quantum state, enabling all scattering histories to be propagated simultaneously via the superposition principle. This quantum state representation enables flexible readout of various imaging modalities, including the primary, i.e., unscattered, image, or images exclusively containing Rayleigh and Compton scattering of specified orders. A quantitative comparison with classically computed reference simulations shows that the proposed quantum walk accurately reproduces radiographic projections, given the limitations of the underlying physical model. These results indicate that quantum circuits for X-ray transport can produce accurate radiographic images and imply that, as quantum hardware scales up, these algorithms could outperform classical Monte Carlo-based approaches in large-scale, scatter-aware virtual imaging studies.
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All authors Anja Heim, Theobald Fuchs, Thomas Lang, Dimitri Prjamkov, Kilian Dremel, Stefan Kasperl, Christoph Heinzl

Sunday 6 September

Emerging Technologies

Phase-cycled randomized benchmarking of quantum processors: recovering hidden classical noise correlations

Mirza Samad Ahmed Baig, Syeda Anshrah Gillani, Abdul Akbar Khan et al. (+1 more)

Randomized benchmarking can hide classical temporal correlations because its Clifford-twirled response is even in the noise phase. For a stationary symmetric telegraph fluctuator, we show that continuous evolution and independent stationary resets at slot boundaries yield identical mean responses for arbitrary fixed idle modulations. We construct an eight-setting phase-cycle measurement of the connected sine-phase covariance under ideal Clifford twirling and classical idle dephasing. This observable vanishes for independent slot noise and fixed detuning without a weak-phase or Gaussian approximation. A closed telegraph response, independent circuit calculations and 800 simulation trials validate the construction and quantify the empirical coverage of a paired bootstrap estimator. A separate conservative confidence set states its finite-sample assumptions. Two acquisitions on an IBM processor compare engineered shared-sign and independently reset phases with identical marginals. Their primary contrasts are 0.254 and 0.211, with empirical 95% intervals [0.177, 0.331] and [0.136, 0.285], respectively; all negative-control intervals include zero. At equal shot and sensingwindow budgets, an ideal Ramsey/echo estimator is more precise in every tested class. The result supplies an explicit connection between a benchmarking identifiability limitation and a controlled correlation measurement. No native or quantum-memory detection is claimed.
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All authors Mirza Samad Ahmed Baig, Syeda Anshrah Gillani, Abdul Akbar Khan, Muhammad Omer Khan

Emerging Technologies

Differentiable Partitioning With Dual-Max 3D Wirelength Model and Hybrid Bonding Terminal Awareness for Optimized 3D Placement

Liwen Jiang, Xu Shi, Rufeng Xiao et al. (+4 more)

Research on 3D integrated circuits (3D-ICs) physical design has expanded rapidly in recent years, driven by the increasing adoption of hybrid bonding and the demand for higher integration density. Continued scaling of hybrid-bonding pitch supports higher vertical interconnect density and finer-grained circuit partitioning in 3D-ICs. Hybrid bonding-enabled 3D-ICs offer substantial benefits in interconnect scaling and system integration, yet tier assignment remains challenging because it jointly determines 3D wirelength and hybrid bonding terminal (HBT) assignment. This paper presents a differentiable partitioning framework that directly optimizes placement-aware tier assignment for 3D-ICs through gradient-based optimization. Discrete tier assignment is relaxed to continuous probabilities, and a Dual-Max 3D wirelength model is introduced as a placement-aware surrogate for tier-specific half-perimeter wirelength (HPWL). In addition, a terminal-aware cutsize penalty gives higher weights to cross-die nets with predicted HBT overlaps, and a local balance penalty discourages regional area overflow on each tier. On ten OpenROAD benchmarks, our method reduces final die-to-die (D2D) HPWL by 8.05% and 14.81% on average relative to hMETIS and TritonPart, respectively. On the seven benchmarks with available CoPlace results, the average HPWL reduction is 10.33%. The source code for the differentiable partitioner and the integrated 3D placement flow is publicly available to support reproducibility.
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All authors Liwen Jiang, Xu Shi, Rufeng Xiao, Changhao Yan, Rujun Jiang, Zhiang Wang, Keren Zhu

Emerging Technologies

multi-Stochastic Core Architecture for Scaling Probabilistic Ising Machines

Chirag Garg, Pratik Brahma, Saavan Patel et al. (+1 more)

Ising Machines offer vast potential to solve NP-hard optimization problems efficiently that are intractable to solve using conventional computing architecture. A lot of these optimization problems fall into statistical learnability and involve finding an optimal solution among many possible, near-analogous configurations, by searching in a non-convex energy landscape. In this context, the probabilistic Boltzmann machine architecture especially PASS (Parallel Asynchronous Stochastic Sampler), explores and models the complex probability landscape pertaining to all possible configurations and excels in finding the ground-state energy solution of these intractable problems. Additionally, the noise-based neuron architecture addresses the limitation of conventional annealing methods, which may get stuck around local minima. Here, we demonstrate a stochastic sampling approach based on Block Gibbs Sampling to integrate multiple asynchronous PASS chips (four in this work), enabling improved scalability. Further, we demonstrate the scaling by mapping 784 nodes Max-Cut problem integrating 256 nodes PASS accelerator manufactured in 14 nm CMOS FinFET technology. PASS-enabled system with Block Gibbs Sampling protocol shows approximately 1000 times speedup for Max-Cut optimization compared to state-of-the-art methods implemented on CPUs and GPUs. The general applicability of this approach is further illustrated by solving a quantum spin chain Transverse Ising system and accurately representing complex probability landscapes. Moreover, our results demonstrate the change in the scaling law to constant in the scaled-PASS accelerator as compared to exponential on GPUs enabling at least 4 orders of magnitude improvement in time-to-solution. Hence, the presented methodology enables the pathway for scaling of asynchronous brain-like dynamics systems that do not follow any clock for its operation.
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All authors Chirag Garg, Pratik Brahma, Saavan Patel, Sayeef Salahuddin

Saturday 5 September

Emerging Technologies · Cross-listed from cs.AR

Towards Enabling Distance-Based Memory Addressing

Ananth Krishna Prasad, Sharad Bhat, Rajeev Balasubramonian et al. (+1 more)

Approximate Nearest-Neighbor Search (ANNS) in high dimensional vector datasets is an application of significant prevalence across different AI applications. However, such an operation is significantly bandwidth limited at large workingset sizes owing to the curse of dimensionality. Traditional indices used to accelerate ANNS rely on search-space pruning as a preprocessing step to alleviate such bandwidth requirement, but such optimization occurs either at the cost of increased bandwidth-inefficiency and/or degradation of search quality. This paper proposes a data-parallel hardware/software mechanism for performing large-scale similarity search in-memory. We propose a novel algorithm to simplify the computation requirement for similarity search across various distance metrics through lightweight primitives to perform a fast and approximate data-parallel brute-force search on the entire vector space. We further build a memory system capable of executing the required operations to generate a distance metric per datapoints, which is then used to enable pruning as a post-processing step. We offer adequate software support for user control over the proposed system. By enabling such search-space pruning as a post-processing step, we achieve near-perfect recall across representative workloads while achieving orders of magnitude performance and energy improvement over state-of-the-art algorithmic approaches on million and billion-scale workloads.
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All authors Ananth Krishna Prasad, Sharad Bhat, Rajeev Balasubramonian, Mahdi Nazm Bojnordi

Emerging Technologies · Cross-listed from quant-ph

Towards Continuous Profiling and Optimization of Quantum-Classical Pipelines

Ayush Bansal, Owen Cochell, Santiago Núñez-Corrales et al. (+4 more)

Quantum applications increasingly execute as multi-stage quantum-classical pipelines, interleaving QPU computation with classical stages like circuit generation, transpilation, layout mapping, quantum error mitigation (QEM), and post-processing. These stages have diverse resource requirements and exhibit stochastic behavior under drifting hardware noises, yet existing workflow frameworks treat them as static, isolated components. We present LLQM (Low-Level Quantum Machine), a profiling-driven meta-framework for quantum-classical pipelines. LLQM decomposes pipelines into fine-grained tasks and continuously profiles their CPU/GPU, memory, QPU, and queue dependencies alongside real-time hardware states. This unified runtime abstraction captures cross-stage resource dependencies and reveals how classical and quantum decisions interact, enabling characterization of their impact on fidelity and resource consumption. We evaluate LLQM using QEM as a representative pipeline stage, on IBM 156-qubit Heron r2 processors with circuits up to 100 qubits and 1e7 transpiled gates. Our results show that continuous profiling exposes runtime bottlenecks and enables hardware-, fidelity-, and workload-aware optimizations.
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All authors Ayush Bansal, Owen Cochell, Santiago Núñez-Corrales, Marcos Frenkel, Seetharami Seelam, Apoorve Mohan, Tianyin Xu

Friday 4 September

Emerging Technologies · Cross-listed from cs.AI

The Normalization of Deviance in AI Development

Emilio Barkett, Alexander Kimpton, Daniel Graham et al. (+1 more)

Work on the risks of artificial intelligence has focused predominantly on capability risk: the danger that systems become too powerful, too autonomous, or too misaligned with human values. Far less attention has been paid to the organizational level—to whether the institutions building these systems are themselves predisposed to drift toward failure. This paper argues that they are. Regardless of how capable AI systems become, the organizations building them face the same structural dynamics that preceded past major technological disasters. Drawing on case studies of the Space Shuttle Challenger, the Three Mile Island accident, and the Boeing 737 MAX crashes, this paper identifies the common structural mechanisms preceding each failure and maps them onto contemporary AI development. The findings suggest that existing safety infrastructure may provide less protection than it appears, as organizations can complete safety processes in full compliance and still produce catastrophic outcomes. The pre-disaster period of AI development is still underway; the purpose of this paper is to make these dynamics legible while they can still be interrupted.
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All authors Emilio Barkett, Alexander Kimpton, Daniel Graham, Yusuf Kundgol

Emerging Technologies · Cross-listed from quant-ph

SAQC: A SAT-Aware Compilation Framework for QAOA-Based Quantum Optimization

Till Schnittka, Julie Maria Raju, Abhoy Kole et al. (+1 more)

The Quantum Approximate Optimization Algorithm (QAOA) is a promising variational approach for solving Boolean satisfiability (SAT) problems. Existing SAT-to-QAOA workflows first translate Boolean formulas into penalty Hamiltonians before applying generic quantum compilation, thereby discarding SAT-specific information such as clause structure, logical operators, and variable dependencies. Consequently, subsequent compiler optimizations cannot exploit the underlying Boolean formulation. This paper presents SAQC, a SAT-aware compilation framework that introduces a SAT Intermediate Representation (SIR) to preserve Boolean structure during compilation. The proposed framework supports both CNF and XOR-extended CNF (eCNF) formulations and performs SAT-aware optimizations including clause rewriting, dependency analysis, and clause scheduling prior to quantum lowering. Building on the optimized SIR, SAQC provides a unified framework for both penalty Hamiltonian generation and direct clause-to-ansatz synthesis, together with ansatz optimizations based on relative-phase decomposition, ancilla-assisted synthesis, and dynamic uncomputation. Experimental results demonstrate significant reductions in circuit depth, two-qubit gate count, and compilation time compared with conventional Hamiltonian-based workflows while remaining compatible with existing quantum compilation frameworks.
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All authors Till Schnittka, Julie Maria Raju, Abhoy Kole, Rolf Drechsler

Emerging Technologies · Cross-listed from quant-ph

Towards Scaling Quantum Fine-Tuning of Foundational Time Series Models for Classification

Sang Hyub Kim, Julien Baglio, Rajiv Krishnakumar et al. (+7 more)

Time-series foundation models produce rich embeddings, but whether quantum models can exploit them, and how far hybrid classical-quantum architectures scale, remains unclear. We address this by fine-tuning Chronos for power-grid event classification (PSML-5) with a quantum head on the model's embeddings. Grouping embeddings by physical sensor type before summarization already surpasses the best published baseline built for this benchmark, and with finer-grained features the quantum head outperforms a larger classical multilayer perceptron on identical inputs by 1.7-2.0 percentage points of balanced accuracy. Yet the gains saturate: past a point, feeding more information to the same fixed-width register yields no improvement. We show the bottleneck is neither the supply of information nor circuit expressiveness, but the bandwidth of the data intake. To overcome this limitation, we introduce the wing module, a self-contained few-qubit circuit that feeds additional information into the core circuit through a sparse, one-way coupling. Under a preregistered four-seed protocol, we attach wings to a fixed 12-qubit core with fixed features. Balanced accuracy increases with each added wing, from 83.6% with no wings (13 qubits, including a post-selection qubit) to 85.2% with two (19 qubits). Ablations establish that a circuit enlarged without new information gains nothing, while a wing fed information from the wrong sample harms accuracy. These results reframe scaling for quantum fine-tuning: added qubits help when they carry added inputs, not merely more parameters. Wings offer a modular and stable route to widening that bandwidth.
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All authors Sang Hyub Kim, Julien Baglio, Rajiv Krishnakumar, Chi Chen, Oliver Knitter, Jonathan Mei, Claudio Girotto, Masako Yamada, Frederik F. Flöther, Martin Roetteler