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Computer Science Hardware Architecture

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Wednesday 14 October · still arriving

Hardware Architecture

STISA: A 0.16 GOPS/W/PE Single-Shot Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design

Kainan Wang, Chengyi Yang, Lei Liu et al. (+4 more)

Spiking neural networks (SNNs) offer great potential for low-power intelligent computing owing to their event-driven nature, yet their deployment is limited by high inference latency and inefficient hardware utilization caused by temporal dependencies. Existing accelerators struggle to balance timesteps, accuracy, and energy efficiency, while hardware-oriented timestep compression remains underexplored. To address these challenges, this work presents STISA, a unified algorithm-hardware co-design framework featuring: (i) a Temporal Splitter Compression (TSC) technique with a Temporal Split Structure (TSS) to reduce temporal redundancy while preserving network dynamics; (ii) a hardware-efficient spatiotemporal parallelism scheme, which co-optimizes dataflow and architecture through a Temporal-Prioritized Output-Stationary (TPOS) mapping and a flexible Block-Mux Streaming (BMS) architecture; and (iii) a joint TSC-TPOS-BMS co-optimization framework featuring a bandwidth-aware resource allocation strategy to achieve balanced accuracy, latency, and energy efficiency across diverse network architectures. On the algorithmic side, TSC reduces synaptic operations by 24.44%-51.71% while achieving competitive accuracies of 96.38%, 81.10%, 68.51%, and 82.40% on CIFAR-10, CIFAR-100, ImageNet, and DVS-CIFAR10, respectively. On the hardware side, FPGA prototypes deliver up to 7.99 speedup, 30.4% power reduction, and 30.1% LUT reduction. Compared with state-of-the-art SNN accelerators, STISA achieves 0.16 GOPS/W/PE, demonstrating its scalability and superior energy efficiency for real-time SNN inference under constrained hardware resources.
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All authors Kainan Wang, Chengyi Yang, Lei Liu, Chengting Yu, Yee Sin Ang, Bo Wang, Aili Wang

Hardware Architecture

CAFE: Conducting-Cell-Aware Adaptive Differential Encoding for Robust DNN Inference in FeFET-Based Compute-in-Memory

Wenshuai Yao, Wenyong Zhou, Hanyong Shao et al. (+3 more)

Ferroelectric field-effect transistor (FeFET)-based compute-in-memory (CIM) promises energy-efficient deep neural network (DNN) inference, but device variation can severely degrade bit-sliced CIM accuracy. Prior works either rely on hardware modifications or treat such variation as generic noise, overlooking a key FeFET asymmetry: negligible off-state leakage makes errors dominated by conducting on-state cells. This asymmetry is amplified by two's-complement sign extension, which maps small negative values to high-significance bit slices and magnifies their errors during shift-and-add reconstruction. In this paper, we propose CAFE, a conducting-cell-aware adaptive differential encoding framework built upon this FeFET-specific asymmetry. CAFE introduces C$^2$AM, a bit-significance-weighted conducting-cell activity metric that predicts output deviation and inference accuracy degradation under FeFET device variation. Guided by C$^2$AM, CAFE applies differential weight and activation encoding to eliminate sign-extension-induced conducting-cell amplification. To balance robustness and cost, CAFE performs type-wise encoding enumeration, layer-wise NSGA-II search, and post-GA pruning to allocate robust encodings where the robustness-cost trade-off is favorable. Across representative vision and language workloads, CAFE reduces C$^2$AM by up to $28.6\times$; in the main deployment study, it improves accuracy over two's-complement CIM by more than 87 percentage points and approaches full-differential robustness at $1.86$-$2.78\times$ normalized cost, compared with $3.06\times$ for uniform full-differential encoding.
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All authors Wenshuai Yao, Wenyong Zhou, Hanyong Shao, Zhiyuan Ning, Ru Huang, Kechao Tang

Hardware Architecture

ESL-former: Event Sparse Linear Transformer for FPGA-Accelerated Malware Detection

Jun Yang, Yumeng Cao, Yingxuan Xiao et al. (+2 more)

Transformer based intrusion detection has shown strong potential for identifying unknown malware variants, but its deployment on resource constrained edge devices remains difficult due to the high computational and memory cost of self attention. This paper presents an event sparse Linear Transformer framework for malware detection on FPGA edge platforms. Instead of relying on an explicit attention matrix, the proposed method derives token and channel importance directly from the accumulated key value state of Linear Transformer. A contribution aware scoring function is introduced to measure the perturbation of each token or kernel channel to the linear attention state, allowing redundant tokens and low contribution channels to be removed without constructing quadratic attention maps. To translate sparsity into practical hardware acceleration, the proposed design further replaces conventional binary mask based execution with a Top K active token buffer and a hardware compaction unit. The selected active tokens and channels are reorganized into dense fixed length data streams, enabling downstream processing elements to execute regular multiply accumulate operations with reduced redundant memory access and control overhead. This design is suitable for low power FPGA based malware detection, where both latency and on chip resource usage are critical. Experimental evaluation demonstrates that the proposed sparse Linear Transformer can reduce hardware cost while preserving malware classification accuracy.
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All authors Jun Yang, Yumeng Cao, Yingxuan Xiao, Changhong Li, Shangru Zhou

Hardware Architecture

MFSA: A Multi-Format Systolic Array with Native Micro Scaling Support

Jiayi Wang, Kearnan Bishop and Ang Li

AI workloads increasingly employ low-precision formats such as BF16 / FP16, FP8 variants, FP4, Micro Scaling (MX), and INT modes across models, layers, and execution stages to balance accuracy, memory footprint, and throughput, which in turn requires hardware to support these formats in a flexible and efficient way. We present MFSA, a weight-stationary multi-format systolic array that achieves area efficiency through two architectural choices. At the PE level, MFSA uses dot-product-accumulator-based processing elements extended from an existing open-source trans-precision FPU to support reduced-precision formats (FP32/FP16/BF16/CFP8/FP4/INT16/INT8/INT4) with a shared datapath and proportional throughput scaling. At the array level, MFSA employs Online Block-Scale Rebasing (OBSR) for block-scaled formats, which folds each block scale into the running FP32 partial sum at block boundaries without adding a second cross-block accumulator, thereby reducing the additional overhead of block-scaling support. In TSMC 28 nm at 1 GHz, matched-throughput BF16/FP8/FP4 cascaded FMA-PE baselines are 1.5x/2.5x/4.5x larger than the single-format DPA-PE, the gap growing with subword parallelism. A routed 16x16 MFSA reaches a peak 0.5/1/2/4 TOPS of FP32/BF16/FP8/FP4, and OBSR cuts the incremental MX overhead by 64.2% in area and 67.5% in energy versus a naive MX implementation baseline, without hurting the numerical stability on real LLM traces. Adding support for all other formats based on a BF16+CFP8 systolic array costs 25.7% additional area. OBSR also extends to non-power-of-two block scales: folding the fractional part of an E4M3 scale into the MFPE dot product supports NVFP4 alongside OCP MX for 11.8% area and 7.3% power over a CFP8+FP4 base, less than half the cost of a naive implementation.
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Tuesday 13 October · still arriving

Hardware Architecture

TALU: A Reconfigurable Tiled-ALU Grid for RISC-V

Ali Emre Oztas, Can Erim Karsal, Mahir Demir et al. (+1 more)

Lane-based RISC-V vector processors exploit data parallelism well but pay a recurring cost for two common patterns: reductions, which require a separate tree pass, and deep dependent expression chains, which cannot be fused and are issued as serial vector instructions. We present TALU, a 5-stage RISC-V core whose execute stage is an NxN grid of registered ALU tiles instead of a single ALU. The grid is a reconfigurable, feed-forward spatial fabric: tiles route operands only from non-backward neighbours, and added diagonal forwarding lets a reduction collapse spatially. A minimal custom extension configures the per-tile operation, routing, and per-tile constants, and streams operands through the array. On a single fabric, TALU runs ordinary scalar code, single deep-path expressions, and multi-lane vector kernels. On the benchmark suite of the RISC-V2 vector processor, TALU is 1.8-5.5x faster than RISC-V2 and 4.5-15.5x faster than Vicuna at equal lane count, with a reduction cost (dot{\div}add) of 1.05x versus 1.96x and 1.26x for the vector cores. A retimed implementation places and routes at 1.03 GHz in 45 nm in 0.30 mm2, half the area of RISC-V2.
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All authors Ali Emre Oztas, Can Erim Karsal, Mahir Demir, Mikel Luján

Hardware Architecture

AMAX: Accuracy-Aware Multi-Loop Asymmetric Perforation for Heterogeneous Architectures

Amna Hassan, Paul Danielse, Anuj Pathania et al. (+2 more)

Thermal constraints in heterogeneous multi-core systems can significantly degrade performance, as conventional techniques such as dynamic voltage and frequency scaling (DVFS) and task migration introduce overhead under high utilization. Approximate computing, particularly loop perforation, can mitigate this overhead by reducing computation at the cost of accuracy loss. However, existing approaches typically apply a uniform perforation rate across all loops, ignoring loop-specific sensitivity. We propose AMAX, an accuracy-aware multi-loop asymmetric perforation framework that reduces the combinational design space through loop-wise profiling and multi-objective configuration selection, and dynamically adapts the resulting configurations at runtime according to performance requirements. Experiments on PARSEC benchmarks show that AMAX achieves up to 0.85 improvement in normalized accuracy over symmetric perforation for the same performance targets.
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All authors Amna Hassan, Paul Danielse, Anuj Pathania, Andy Pimentel, Semeen Rehman

Hardware Architecture

CacheSmith: Accurate RAG Serving under Latency SLOs with Adaptive KV Reuse

Xinyue Ma, Damin Lee, Aashaka Shah et al. (+1 more)

This paper presents CacheSmith, a KV cache reuse system for RAG prefill that maximizes quality-gated SLO attainment. While context caching lowers prefill latency by reusing precomputed KV states for retrieved chunks, it misses cross-chunk attention that a full prefill would compute over concatenated inputs. Prior selective recomputation schemes tackle this problem but enforce static, one-size-fits-all configurations that fail to effectively handle request heterogeneity or dynamic latency budgets. CacheSmith decomposes selective recomputation into a three-phase workflow of WarmUp, Probe, and Patch that can be dynamically configured to exploit a wide range of cost-accuracy trade-offs. At serving time, an SLO-aware scheduler in CacheSmith forms batches to mitigate inter-request interference during layer-by-layer prefill, while a budget-aware planner configures recomputation phases across the batch to maximize the number of requests satisfying both generation quality and latency targets. Both components make fast, solver-free decisions over profiled cost-accuracy bands. On four benchmarks across varying arrival rates and burstiness levels, CacheSmith improves quality-gated SLO attainment by up to 27.5%, over four state-of-the-art baselines.
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All authors Xinyue Ma, Damin Lee, Aashaka Shah, Myeongjae Jeon

Hardware Architecture · Cross-listed from cs.NI

HILO: Enabling Low-power, Dual-Band Communication using Tunnel Diode Oscillators

Dhairya Shah, Rajashekar Reddy Chinthalapani, Pramuka Sooriya Patabandige et al. (+1 more)

Wireless communication remains the most power-consuming operation in embedded systems. Low-power transmitters such as backscatter achieve microwatt-scale operation but produce weak signals susceptible to in-band interference and frequency-selective fading, particularly in non-line-of-sight settings. Multi-band transmission can mitigate these effects through spectral-domain redundancy rather than temporal-domain redundancy, improving reliability without sacrificing bitrate or latency. However, conventional multi-band radio transceivers require duplicated RF chains or power-hungry synthesizers. We introduce HILO, a tunnel diode-based frontend that enables dual-band operation from a single circuit. HILO inverts the conventional paradigm: rather than suppressing the harmonics inherent to tunnel diode nonlinearity, it harnesses them. An external device injection-locks the oscillator to a fundamental frequency, simultaneously stabilizing a higher harmonic and yielding two injection-locked carriers without a second oscillator or frequency multiplier. In transmit mode, HILO exploits self-oscillating mixing to modulate both carriers simultaneously; in receive mode, it uses autodyne downconversion at both frequencies. By turning an inherent nonlinearity into a feature, HILO achieves dual-band links while consuming under 210 $\mu$W.
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All authors Dhairya Shah, Rajashekar Reddy Chinthalapani, Pramuka Sooriya Patabandige, Ambuj Varshney

Hardware Architecture · Cross-listed from cs.CR

HULK: An Efficient Algorithm for Enabling Fast Bulk Bitwise Operations on Homomorphically Encrypted Data

Mayank Kabra, Phillip Widdowson, Harshita Gupta et al. (+9 more)

A wide range of important cloud applications, e.g., database analytics, graph analytics, and genome analysis, spend a considerable amount of time performing bulk bitwise operations (e.g., AND, OR, XOR). These applications often operate on highly sensitive data, making data privacy a critical concern. Homomorphic encryption (HE) enables secure computation on encrypted data without requiring decryption, ensuring privacy in untrusted and shared environments. We analyze 13 end-to-end applications across three domains (healthcare, graph, and database analytics) and observe that bulk bitwise operations take 62-100% of the execution time of the healthcare and graph workloads. The key problem is that existing HE approaches perform them with high-latency homomorphic operations (e.g., multiplication or lookup tables) and significantly increase the data size. Our goal is to enable fast bulk bitwise operations on homomorphically encrypted data by designing an efficient HE algorithm that reduces the use of these costly operations. To this end, we propose HULK, which performs two key steps: (1) it constructs bulk bitwise operations using low-cost homomorphic additions, which compute the Hamming weight of the encrypted operand bits in every slot of a packed ciphertext without any homomorphic multiplication, and (2) it decodes the result of an AND, OR, or XOR from the Hamming weight with a single indicator polynomial, keeping the result in the standard encoding. Across 13 end-to-end applications in healthcare, graph, and database analytics, HULK improves performance over the arithmetic approach used by prior works by up to 7.26x (CPU) and 6.65x (GPU), and on average by 2.32x/1.78x/1.45x (CPU) and 2.08x/1.70x/1.51x (GPU) for healthcare/graph/database analytics. When we increase the reduction depth in a representative application, HULK's speedup grows to 10.10x over the state-of-the-art GPU baseline.
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All authors Mayank Kabra, Phillip Widdowson, Harshita Gupta, Rakesh Nadig, Nisa Bostanc{\i}, Eirini Tzermpou, Rakesh Kumar, Spiros Galanopoulos, Ataberk Olgun, Abdullah Giray Yağl{\i}kç{\i}, Mohammad Sadrosadati, Onur Mutlu

Hardware Architecture

FPGA Based Design And Implementation of Neural Network Compensators for Nanocrystalline MEMS Pressure Sensor

Somsubhra Talapatra, Sudip Ghosh, C Roy Chaudhuri et al. (+2 more)

In this paper the effects of nonlinearity and temperature of nanocrystalline MEMS pressure sensor have been compensated using neural network algorithm which has been implemented on a FPGA chip. The neural network employs back propagation algorithm to train the multilayer perceptron feed forward network that causes an error reduction due to temperature upto the level of 98%. It is realized on FPGA with pipelined architecture for parallel and fast sensing operation. The pressure sensor along with the FPGA based compensation results in an intelligent sensor system capable of high speed and accurate pressure measurement which has been tested for a typical biomedical application.
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All authors Somsubhra Talapatra, Sudip Ghosh, C Roy Chaudhuri, Biplab K Sikdar, Hafizur Rahaman

Monday 12 October

Hardware Architecture

Formal-Verification-Guided Bayesian Optimization for Non-Intrusive Last-Mile Coverage Closure

Chengjia Liu, Priyadarsi Mishra, David Kebo Houngninou et al. (+3 more)

Last-mile functional coverage closure for modern chip designs remains costly because a mature UVM environment exposes many controls while direct hits on the remaining bins are sparse. We present a non-intrusive workflow that closes pre-defined bins in an existing, human-authored functional coverage model; it does not synthesize verification objectives from the design specification. The workflow first uses abstract-syntax-tree (AST) parsing and cone-of-influence (COI) tracing to map each residual target to existing testbench knobs. Under a matched 20-simulation budget, Bayesian optimization (BO) is compared with continued constrained-random verification (CRV) and random search over the same AST/COI-reduced space. Formal reachability then removes only targets supported by complete unreachability proofs, after which retained targets are grouped by formal difficulty and processed by group-specific BO under a second matched 20-simulation budget. Cleanup and grouping never add numerator bins; only simulator coverage artifacts do. On OpenTitan AES, first-pass reduced-space BO reaches 241/271 bins; formal cleanup removes two denominator bins; the integrated post-cleanup stage - difficulty grouping, policy routing, and group-specific BO - adds 20 simulator-confirmed hits, yielding 261/271 raw coverage (96.31%) and 261/269 effective coverage (97.03%). On Entropy Source, first-pass reduced-space BO reaches 2117/2277 bins; formal cleanup removes ten denominator bins; the integrated post-cleanup stage - difficulty grouping, policy routing, and group-specific BO - adds 93 simulator-confirmed hits, yielding 2210/2277 raw coverage (97.06%) and 2210/2267 effective coverage (97.49%). These results characterize the integrated diagnosis-and-search workflow; the present evaluation does not isolate the causal contributions of difficulty classification, policy routing, and post-cleanup BO.
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All authors Chengjia Liu, Priyadarsi Mishra, David Kebo Houngninou, Michael Quinn, Aakash Tyagi, Jiang Hu

Hardware Architecture

When Is RTL Better? Auditing Evaluation Stability with Tool-Grounded Requirement Profiles

Bodong Hou and Zhixin Pan

RTL-generation studies increasingly report functional correctness and post-synthesis quality, yet the evaluator itself is rarely treated as an experimental variable. A candidate can appear better when a security rule, protocol obligation, target context, feasibility gate, uncertainty policy, or provenance constraint is omitted. We introduce tool-grounded requirement profiles: machine-readable contracts binding each requirement's meaning to its executable evidence and comparison rule, together with cross-requirement gates, uncertainty handling, and provenance. We audit evaluator stability by freezing candidate pairs and perturbing only their evaluation profile. In a preregistered controlled pilot with six designs, twelve pairs, three requirement families, six evaluator conditions, and 72 decisions, a generic cell-count evaluator reports unsupported improvement for 6/12 pairs (50%; Wilson 95% interval 25.4 to 74.6%; design-cluster bootstrap interval 25 to 75%). The matched evaluator detects all twelve injected regressions, whereas syntax, generic synthesis, context mismatch, and gate ablation each lose the required distinction for 12/12 pairs. In a separately frozen external validation of all 290 public RTLLM v1.1 text-only candidates, 81/215 evaluable comparisons (37.7%; task-cluster 95% interval 24.8 to 51.4%) yield unsupported scalar improvements, including 72 functional-gate reversals. Separately, 26 OpenROAD-flow-scripts runs show why timing context and activity qualification must be part of the contract. The study does not rank generators; it establishes evaluator configuration as a measurable, auditable source of conclusion instability.
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Hardware Architecture

LocalTrain: Integer-Only Local Learning for Energy-Efficient CNN Training on Edge FPGAs

Shiqi Ding, Xuanyu Liang, Xinyang Liu et al. (+4 more)

Local learning reduces cross-layer training dependencies, but an efficient accelerator must still retain operands, accumulate gradients, and select quantization scales. We present an FPGA system that trains a CNN and its regional auxiliary classifiers using a shared integer matrix engine. Compact errors are expanded on chip, gradients are folded tile by tile, and historical scales permit direct output conversion. At 200 MHz, the KV260 prototype achieves 76.57% accuracy on CIFAR-10 and 91.85% on SVHN at approximately 4.20 W mean module power. Effective matrix throughput is 31.22 and 31.57 GMAC/s, respectively. Against the same integer method on Jetson Orin Nano, measured training energy is 40.4% and 42.1% lower, with $1.86\times$ and $1.82\times$ longer runtime; measurements use the respective platform power domains. Selected state checks and matching complete-run prediction counts support functional agreement with the software reference.
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All authors Shiqi Ding, Xuanyu Liang, Xinyang Liu, Boyang Li, Zhiqiang Que, Guosheng Hu, Jiayang Li

Hardware Architecture

FORGE: Procedural Weight Generation for Sparse MoE Inference

Chanyoung Moon, Travis Pence, Daisuke Yamada et al. (+4 more)

We introduce FORGE (Fast On-chip Rotor Generation for Experts), a procedural weight generation system for Sparse Mixture-of-Experts (MoE) inference. Rather than storing and loading every expert weight tensor from HBM, we show how a compact accelerator inside each Streaming Multiprocessor can regenerate them on-the-fly from $O(\log^2 d)$ rotor parameters per projection. Per replaced layer, gigabytes of stored expert weights are approximated with under a megabyte of seeds. This addresses the dual memory bottleneck of autoregressive Sparse MoE decode, where per-expert FFN operations are HBM-bandwidth-bound at small routed-token counts and the aggregate expert footprint forces multi-node Expert Parallelism (EP) with all-to-all traffic. We realize the approach as the Rotor Generation Unit (RGU), a fixed-function datapath that generates FFN weight tiles without competing with Tensor Core execution. With 30% of the MoE FFN layers replaced across five Sparse MoE models, we estimate 1.3-2.8x higher system throughput at matched GPU count and 1.10-1.15x lower per-user decode latency at short context. In exchange, downstream accuracy on three model families falls below that of the same model fine-tuned without rotor replacement, and the replacement ratio controls this tradeoff. FORGE also expands KV cache capacity by 1.2-2.6x. It is agnostic to the bit width at which weights are stored, so it can compose with quantization. The RGU is fully implemented/verified in SystemVerilog at ~0.9% SM area overhead (0.032 mm^2/SM, 7nm).
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All authors Chanyoung Moon, Travis Pence, Daisuke Yamada, Jiaqi Mo, Yanxin Zhang, Vikas Singh, Karthikeyan Sankaralingam

Hardware Architecture · Cross-listed from cs.CR

Resource-constrained Remote Attestation of Smart Meters Using Merkle Trees in a Trusted Execution Environment

Amirhossein Shakiba, Hamid Reza Ghaeini and Sadegh Dorri Nogoorani

Smart meters are pivotal to the functioning of smart grids, as they measure and transmit energy consumption data that includes sensitive information about household energy usage patterns. While this data offers significant financial benefits, it can also reveal detailed insights into residents' daily routines, making the security of smart meters a critical concern. This paper introduces a novel remote attestation method for smart meters that ensures the integrity and privacy of data exchanged between smart meters and central servers while detecting unauthorized tampering. Our approach structures the communication data into a Merkle Tree-a hash data structure that facilitates efficient data integrity and authenticity verification. All operations involved in constructing the Merkle root and hashing critical data are executed in the secure environment of a Trusted Execution Environment (TEE) using OP-TEE, thereby maintaining the integrity and security of the smart meter's data. Comparing our experimental results with the related works highlights the superiority of our method in terms of resource efficiency, security robustness, and the feasibility of implementation on smart meters and resource-constrained devices, thereby enhancing the overall security and reliability of smart grid systems.
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Hardware Architecture

SafeDSE: Joint Exploration of Safety Architecture Patterns, Mapping, and Scheduling for Dataflow Applications With Safety Arguments (Extended Version)

Fatemeh Bahrami and Seyed-Hosein Attarzadeh-Niaki

Embedded platforms increasingly host safety-related streaming functions next to less critical ones. Whether a safety architecture pattern, such as a doer/checker pair, protects a function depends on the cores that run its components. Their schedule must meet the throughput requirement, and mixing safety integrity levels (SILs) on one core raises development cost. This report presents SafeDSE, a design space exploration framework for synchronous dataflow applications. One declarative constraint model decides the pattern of each actor, the placement that the fault model requires, the static-order schedule, and the platform, and prices SIL promotion. Guards activate the chosen patterns in a fixed graph that holds all of them, and node potentials encode throughput. An independent verifier re-checks every solution, and a generator turns its checks into evidence of a safety argument in Goal Structuring Notation. On 9 benchmark instances under period bounds, no rule that fixes patterns before mapping was both always feasible and never more expensive under conservative pricing, while joint exploration was. In the generated arguments, 49 to 62% of the leaves cite verifier checks; the rest are claims a mapping cannot discharge. Optimality within the model was proven for all synthetic graphs with up to 16 actors. This extended version adds the full model, the verifier and generator in detail, the complete catalog and parameters, and a proof of the potential characterization. It also reports every experiment per instance, a mutation analysis of the verifier, and the negative results of the development.
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Hardware Architecture

LizTail: Unifying Shape Adaptation and Spatial Parallelism with Segment-Reconfigurable Systolic Arrays

Gang Liu, Chen Yang, Junyan Hu et al. (+2 more)

Systolic arrays are widely used to accelerate neural-network inference, yet fixed two-dimensional arrays struggle with the substantial diversity in both matrix geometry and available parallelism across CNNs and Transformer-based large language models. This mismatch is particularly severe for skinny matrices, small-batch autoregressive decoding, and operators containing multiple independent partitions, leading to low processing-element (PE) utilization and repeated spatial folding. Existing reconfigurable arrays typically improve either shape adaptation or distributed execution, whereas supporting both through fine-grained routing incurs considerable interconnect, buffering, and control overheads. We present LizTail (named after lizard tail autotomy, where predefined fracture planes allow segments to detach and remain independently active, analogous to LizTail's predefined reconfiguration boundaries), a multi-mode systolic array that enables constrained segment-level reconfiguration by partitioning a $128\times128$ array into 32 regular $128\times4$ segments and adding connectivity only at predefined endpoints. The resulting substrate supports trimming, long-path extension through $180^\circ$ turn-back connections, and distributed execution in which each subarray can itself be trimmed or extended. Differentiated PE datapaths and segment-aware CEB/SIB buffers provide the required compute and data-delivery flexibility without unrestricted PE-level routing. A hardware-constrained mapper selects the execution organization, dataflow, task partition, and tiling. Across representative workloads, LizTail achieves geometric-mean speedups of $5.02\times$ on CNN inference and $25.67\times$ on LLM decoding over a TPU-like array, while reducing EDP by up to $38.23\times$. LizTail is open-sourced at https://github.com/kmjbwxa/LizTail.
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All authors Gang Liu, Chen Yang, Junyan Hu, Jianguo Chen, Lixin Duan

Sunday 11 October

Hardware Architecture

O-SCOPE: a Raspberry Pi Pico oscilloscope

Gabriel Andrecut and Mircea Andrecut

In this paper we provide an introduction to some of the efficient features of the Raspberry Pi Pico (RP2) family of microconroller boards (RP2040 and RP2350). More exactly, we show how to use PIO (Programmable Input/Output) and DMA (Direct Memory Access) to program the RP2 boards for efficient DAC (Digital to Analog) and ADC (Analog to Digital) conversions. Using OP-AMPS (Operational Amplifiers) we also show how to build a minimal electronic frontend interface for signal input/output. Finally, we integrate all these components into a product, the O-SCOPE, which is a practical and easy to use oscilloscope and wave function generator. The RP2 component of the O-SCOPE is built using Micropython, while the user interface is developed using vanilla Javascript and it runs on the web browser of any computer, interacting with the RP2 board via the Web Serial API. The O-SCOPE web interface is hosted on GitHub Pages such that it is directly accessible everywhere using a web browser, such that no local installation is required. Also, the RP2 software component is freely distributed on GitHub using the UF2 (USB Flashing Format) mass storage file, and it can be installed by simply dragging the file on the RP2 boards. These features make the O-SCOPE easily accessible, transforming it into a very low cost and useful tool for laboratories everywhere in the world.
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Hardware Architecture

GarageWorks: A Shared Testbench Abstraction for Software Simulation and FPGA Testing

Kazutomo Yoshii

GarageWorks is a lightweight FPGA testing framework that enables the same cocotb testbench to be used for both software RTL simulation and FPGA-accelerated hardware simulation. A shared abstraction hides backend-specific interfaces, while synthesizable Advanced eXtensible Interface (AXI) dispatchers provide design-under-test (DUT)-specific control and test operations on the FPGA. GarageWorks is intended for rapid bare-metal testing of standalone designs and on-chip processing logic for scientific sensors, rather than full SoC-level prototyping. The framework has been validated on AMD Alveo V80 FPGAs with several internal designs and provides initial support for AI-assisted generation of DUT-specific test components.
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Hardware Architecture

Integration, Enhancements and Evaluation of Memory Simulators

Pouya Esmaili-Dokht, Arash Yadegari, Victor Xirau et al. (+5 more)

Currently, there is no common methodology or set of practices for evaluating memory-system performance in integrated simulation infrastructures. As a result, studies adopt different evaluation approaches, which can lead to conflicting conclusions even for the same simulation infrastructure. We propose a validation methodology that evaluates memory-system performance from three complementary views: the memory simulator, the CPU–memory interface and the simulated application. We use these views to detect, understand and correct memory-simulation inaccuracies arising from simulator integration and simplified modeling of microarchitectural features. The methodology reveals that the application's perception of memory performance can become effectively decoupled from the detailed memory simulation. Most importantly, we identify and correct a fundamental memory-model mismatch between delayed-response cycle-accurate memory simulators and ZSim, a representative parallel CPU simulator. We demonstrate the broader applicability of these enhancements by applying them to ZSim integrations with Ramulator 2, DRAMsim3 and DRAMSys 4, covering all major public cycle-accurate memory simulators. After the corrections and enhancements, all integrations reproduce the main bandwidth–latency trends and key characteristics of the actual system. Across the evaluated simulators, STREAM bandwidth differs from actual-hardware measurements by less than 5% in most experiments, while pointer-chase latency remains 15–18% lower than on actual hardware. All simulator enhancements are released as open source.
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All authors Pouya Esmaili-Dokht, Arash Yadegari, Victor Xirau, Julian Pavon, Hamid Sarbazi-Azad, Adrián Cristal, Eduard Ayguadé, Petar Radojković

Hardware Architecture · Cross-listed from cs.LG

Heterogeneous Structured Pruning Under Resource Constraints for Hardware-Efficient Large Language Models

Cameron Barker, Andreas Paraskeva, Jan N. van Rijn et al. (+2 more)

Training-free pruning removes weights from pretrained large language models to reduce their deployment cost. However, existing approaches typically consider only the total number of retained weights. Consequently, their pruning decisions do not account for how target hardware stores and processes those weights. These methods select a sparsity structure in advance and apply it uniformly to all projections, rather than accounting for how each structure trades pruning error against latency and memory across sublayers. We propose Heterogeneous Structured Pruning (HSP), a hardware-aware pruning framework that combines two components: (i) a heterogeneous search space of dense, unstructured, 2:4, block-sparse, and head / channel (H/C) pruning options and (ii) structure-regularising constraints based on latency and memory models. Our contribution generalises existing importance-based methods: a global solver selects one option per sublayer to minimise proxy pruning loss under a resource budget, thereby assigning each projection a structure and density. We evaluate HSP on OPT and LLaMA models for an NVIDIA Jetson Orin Nano Super edge device, where it improves the quality-resource frontiers over training-free baselines. A project page and updated links for the related code is maintained at: cameronbarker.me/publications/hsp.
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All authors Cameron Barker, Andreas Paraskeva, Jan N. van Rijn, Elliot J. Crowley, Henry Gouk

Hardware Architecture · Cross-listed from physics.optics

Comparative Robustness of Mach-Zehender and Microring Photonic Matrix Multipliers Under Laser RIN and Thermal Drift

Andreas Falkenberg

Photonic matrix multipliers can accelerate neural-network inference, but their practical utility depends on how optical weight elements respond to source noise, thermal variation, and calibration error. This paper compares Mach-Zehnder modulator (MZM) and microring-resonator (MRR) implementations under laser relative-intensity noise (RIN), column-wise thermal/phase drift, and their joint action. Two CIFAR-10 classifiers - a compact four-layer CNN and ResNet-8 - are mapped to matched photonic multiply-accumulate chains using common source-distribution, detection, numerical, and calibration assumptions. Both architectures reproduce the same zero-perturbation baseline for each workload: 79.5% classification accuracy for the Small CNN and 70.0% for ResNet-8. Robustness is then evaluated using separate RIN-only and drift-only sweeps and a full two-dimensional RIN-drift grid, with dimensionless RMS perturbation levels extending from 0.5% to 20%. The analysis reports classification accuracy, class normalized confusion matrices, rolling-accuracy traces, one-dimensional robustness curves, and multidimensional response surfaces. Device equations and parameter definitions follow the models implemented in the QPI Labs Photonic Inference Simulator, with shared laser fluctuations propagated as correlated multiplicative noise and slow drift represented as a per-output-column perturbation of calibrated weights. All numerical results are generated from recorded experiment configurations and random seeds. The study provides a controlled system-level framework for comparing interferometric and resonant photonic weight elements while limiting conclusions to the implemented device models, perturbation ranges, calibration policy, and neural-network workloads.
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Hardware Architecture

Stateless Stochastic Computing for Generative AI on Superconducting Logic: A Model-Hardware Co-Design

Mehdi Kamal and Massoud Pedram

Thermodynamic computing lets stochastic physical dynamics carry out a computation and reads out the result as a time average. Recently, thermodynamic computing has been demonstrated on several hardware platforms, including digital CMOS circuits based on stochastic computing. Superconducting single-flux-quantum (SFQ) logic offers very high clock rates and very low switching energy, but it heavily penalizes state, memory, fan-out, and feedback, i.e., exactly the per-neuron accumulators on which such designs rely. We therefore realize thermodynamic computing in SFQ logic through a co-design of a generative model and its circuit in which the datapath holds no state at all. The model is a class-conditional flow-matching image generator, which transforms Gaussian noise into an image of the requested class along a short, deterministic path of four Euler steps; in hardware, these steps are unrolled into a feed-forward pipeline of stochastic bitstream operators, whose output is read out as a time average, as in thermodynamic computing, without any relaxation phase. Each layer of the model is a butterfly-factorized linear map built exclusively from multiplexers that operate on split-unipolar bitstreams. The ReLU activation, which in stochastic computing requires a per-neuron up/down counter (accounting for 60-70% of the JJs in a counter-based design), is replaced by a stateless AND-NOT gate whose one-clock input skew is provided at no cost by SFQ gate-level pipelining. The models are trained directly on the stream representation of the hardware, with a regularizer that bounds the stream gains. Synthesis with an SFQ design flow shows that stochastic streams tolerate relaxed path balancing, which reduces the Josephson-junction (JJ) count of a hard-wired stage by 40-47%.
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Hardware Architecture

The Era of Vibe Tapeout: Dark Age or Golden Age for Analog Circuit Design?

Kentaro Yoshioka

LLM agents now write their own schematic and layout generators, run EDA tools, read the results, and fix the design. This "vibe tapeout" is becoming practical for analog circuits as well. This paper measures how far it has come in two settings. (A) On an open PDK (SKY130), a cloud LLM agent designed an 11-bit, 5.12-MS/s SAR ADC from its specification. The agents produced DRC- and LVS-clean macros and met the specification after parasitic extraction (PEX). In particular, under the condition in which the agent received a sanitized reference design derived from our 65-nm design (vibe porting), it produced the best layout in the shortest time. Its area was 1/1.6 to 1/2.8 of that of the conditions without a reference. This condition reached signoff without human intervention. The agents also identified the causes of post-PEX degradation (CDAC wiring coupling and common-mode-dependent comparator offset) by their own experiments. On the other hand, agents sometimes reported false passes, and verification independent of the design agent was essential. (B) A commercial PDK is under NDA and cannot be given to a cloud LLM. We therefore evaluated local LLMs running on university servers with a six-task benchmark on a commercial 65-nm CMOS PDK. Kimi K3 passed five of the six tasks, while MiniMax M3 passed two. Neither solved the debugging task, which requires finding the cause from symptoms. Finally, we discuss the prospects for extending vibe tapeout from ADCs to entire SoCs, and ask whether vibe tapeout is a dark age or a golden age for analog design. Our answer is that it is a golden age for designers who know what to verify.
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Saturday 10 October

Hardware Architecture

MoSAIC: Learning DAG Scheduling Heuristics from Optimal Schedules through Motif-Aware Recovery and LLM-Guided Reasoning

Shiva Ahir, Hashmath Shaik, Alex Doboli et al. (+2 more)

Efficient task scheduling in heterogeneous computing systems remains a fundamental challenge in embedded and high-level synthesis flows. This paper presents MoSAIC (Motif-aware Scheduling with AI-driven Cognition), a learning-based framework that bridges the gap between exact and heuristic scheduling approaches for DAG-based applications. The system uses the reasoning capabilities of large language models (LLMs) to learn the relationships between DAG structures and scheduling priority functions. The framework first leverages the OR-Tools CP-SAT solver [4] to generate optimal schedules, which are then used to supervise the learning of compact priority-based scheduling functions through Bayesian Optimization. These learned heuristics capture relationships between scheduling decisions and structural graph features such as rank, depth, and fanout, enabling the construction of a reusable knowledge base across diverse DAG instances. Experimental results across synthetic graph families and real-world benchmarks, including PolyBench and MachSuite, show that the learned heuristics consistently improve over classical approaches such as HEFT [2], while maintaining low runtime overhead. The results indicate that combining optimal supervision with learning-based generalization provides a practical approach for scalable and adaptive task scheduling.
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All authors Shiva Ahir, Hashmath Shaik, Alex Doboli, Nadeem Yaseen, Simona Doboli

Hardware Architecture

Programmable Data Layouts via On-The-Fly Data Transformation

Cole Strickler, Renato Mancuso, Manos Athanassoulis et al. (+1 more)

The performance of modern computing systems is heavily bottlenecked by the widening gap between processing throughput and main memory latency, a problem exacerbated when an application's logical data access patterns misalign with the physical layout of data in memory. To address this, we propose a hardware-software co-design framework comprising the Data Transformation Language (DTL) and the Data Transformation Unit (DTU). DTL allows programmers to concisely express complex data layout reorganizations, which the compiler translates into efficient hardware routing configurations. The DTU, a hardware engine logically situated between the Last-Level Cache (LLC) and main memory, transparently evaluates these configurations on-the-fly to gather scattered data elements into dense, logically contiguous cache lines. By converting explicit layout transformations into virtual views, this approach eliminates the need for explicit data materialization in software. We evaluate the DTU within a quad-core RISC-V SoC using FireSim, demonstrating substantial improvements in execution speed and memory efficiency.
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All authors Cole Strickler, Renato Mancuso, Manos Athanassoulis, Heechul Yun

Hardware Architecture

GaborFlow: Hardware-Software Co-Optimization of Gabor Filter Accelerator Design

Priyanka Agarwal, Pruthvi Parate, Raghav Khurana et al. (+1 more)

Brain tumor classification from MRI scans represents a critical challenge in medical imaging, where accuracy directly impacts patient outcomes. This paper introduces GaborFlow, a novel hardware-software co-optimization framework that revolutionizes the design of the Gabor Filter accelerator for generating feature maps to enhance brain tumor detection. Unlike conventional approaches that rely on fixed filter parameters, our method employs trainable Gabor coefficients within a carefully optimized range, integrated with an EfficientNet-B0 backbone CNN architecture. The innovation lies in the synergistic combination of software optimization through Bayesian hyperparameter tuning and hardware efficiency through precision-optimized multipliers. Our GF baseline accelerator achieves remarkable results, with 98.6% classification accuracy, 28.08% power benefits, and 48.83% footprint savings compared to state-of-the-art implementations, demonstrating that medical AI can be both highly accurate and energy-efficient. The hardware design files are made freely available for easy adoption and further usage by the researchers and designers.
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All authors Priyanka Agarwal, Pruthvi Parate, Raghav Khurana, Madhav Rao

Hardware Architecture

"Is Low Power Enough?" Rethinking Energy Efficiency in High-Fidelity Sensing

Chae Young Lee, Lan Mei, Jesse Fonseca et al. (+1 more)

For two decades, long-lived sensor nodes have been built from the lowest-power parts, because their scalar readings take only milliseconds to acquire and send. Scientists now want higher fidelity data from the field, such as images and audio, and these observations break that rule: a low-power microcontroller stays awake for seconds to read, store, and transmit each one, so low power is no longer low energy. We argue that long-lived, high-fidelity nodes should instead be built around a more capable microcontroller, provided the whole board sleeps deeply. We revisit two principles from early sensor networks, "race to sleep" and "talk less", for high-fidelity data and on-device AI, and test them by comparing the STM32N6, which pairs a fast core with a neural accelerator, against the low-power Apollo4 Plus. Although the STM32N6 draws 1.9x more power, it completes an observation (capture, storage, on-board detection, and a LoRa transmission) 9.9x faster and so uses 5.2x less energy. On the same model, it runs inference with 3.2-11.4x less energy, and it fits models over 23 points more accurate. A high-fidelity node lives longest when it finishes quickly, sleeps deeply, and sends only what matters.
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All authors Chae Young Lee, Lan Mei, Jesse Fonseca, Zerina Kapetanovic

Hardware Architecture

HADES: A Programmable Processing-Near-Memory Engine for Binary Similarity Search

Pranav M

Moving operands to a processor can cost more than the arithmetic performed on them, and for small binary similarity and search workloads data movement can dominate. We present HADES, a programmable processing-near-memory engine built around one shared 32x32-bit 2R1W register-file macro that holds both data and program. Twelve 16-bit opcodes, three working registers and a 32-slot program express ten search workloads in 8 to 19 slots, and SCANP and SCANSEL shorten dual-row and selected scans. A post-layout 2x2 Tiny Tapeout implementation closes timing at 40 MHz with 26,968 square microns of standard cells beside a 15,744 square microns macro. All HADES results come from RTL or gate-level simulation of this implementation, and HADES energy is estimated. Against ESP8266 and ESP32 microcontrollers running plain C, and with an ideal host, HADES answers a resident query 10x to 32x and 2.2x to 11x faster, respectively. End to end, it wins at the evaluated batch sizes of B = 16 and B = 256 against both boards and loses the single-query (B = 1) runs to the ESP32. An Arduino Nano runs a restricted subset. Kernel power stays within about 2% of a spin loop on all three boards. These results hold for plain-C baselines under the evaluated conditions. At this scale the control and instruction storage fit around a shared memory macro, while the byte-wide interface and the loading path remain significant costs.
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Friday 9 October

Hardware Architecture

From Prompts to Silicon: Scaling LLM-Assisted Chip Design with the AI Hardware Design League

Parsa Mirfasihi, Harish Kumar Dharavath, Muhtasim Alam Chowdhury et al. (+5 more)

The semiconductor workforce shortage has renewed interest in making chip design accessible to students without conventional very-large-scale integration (VLSI) training. We present the AI Hardware Design League (AI-HDL), an international, project-based competition in which students use Large Language Models (LLMs) to generate and iteratively refine Verilog while simulation, synthesis, timing analysis, security review, and physical verification provide the engineering feedback needed to validate the result. Across two annual cycles, AI-HDL grew from 172 to 604 participants and from 40 to 108 teams, reaching 30 universities, six community colleges, and 19 countries. In the 2026 cohort, 68.7% of participants reported no prior Verilog experience. Twenty-two teams completed the four design phases and reached final evaluation. Two division-winning designs completed physical sign-off in the SkyWater 130 nm (Sky130) process, passing design-rule checking and layout-versus-schematic verification with zero violations before being submitted for fabrication. These results show that an LLM-assisted, tool-grounded workflow can be deployed at substantial scale while also revealing that completion, rather than initial access, remains the principal challenge. AI-HDL materials and finalist artifacts are released to support replication and future study.
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All authors Parsa Mirfasihi, Harish Kumar Dharavath, Muhtasim Alam Chowdhury, Sujan Ghimire, Banafsheh Saber Latibari, Rozhin Yasaei, Pratik Satam, Soheil Salehi